منابع مشابه
Hierarchical Delay Test Generation
Delay testing is used to detect timing errors in a digital circuit. In this paper, we report a tool called MODET for automatic test generation for path delay faults in modular combinational circuits. Our technique uses precomputed robust delay tests for individual modules to compute robust delay tests for the module-level circuit. We present a longest path theorem at the module level of abstrac...
متن کاملSwitch-level delay test
Gate-level models are usually used to generate tests for circuits containing non-primitive CMOS gates. It is shown that tests generated using these models and classical conditions for robust path delay testing can fail to detect delay faults in such circuits. A new delayindependent, switch-level delay test methodology, called -robust testing, is proposed that de nes new entities called targets ...
متن کاملDelay Test with Embedded Test Pattern Generator
A new on-chip embedding mechanism to improve fault coverage in scan-based delay test is proposed. A major problem of scan-based delay test techniques is that they may not provide good fault coverage as many valid test pattern pairs cannot be launched. In the proposed method, the initialization vector is shifted into the scan chain, and then the activation vector is generated by selectively inve...
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BACKGROUND The purpose of this study was to provide some evidence of the validity of a modified shuttle test (MST) by comparing performance on the MST with peak oxygen consumption (VO2peak) measured during a treadmill test in a group of adult patients with cystic fibrosis. METHOD Twenty patients with stable cystic fibrosis performed a ramped maximal treadmill test (STEEP protocol) and the MST...
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ژورنال
عنوان ژورنال: Nature
سال: 1987
ISSN: 0028-0836,1476-4687
DOI: 10.1038/329003d0